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A list of all the posts and pages found on the site. For you robots out there is an XML version available for digesting as well.
Pages
Posts
Future Blog Post
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Blog Post number 4
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Blog Post number 3
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Blog Post number 2
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Blog Post number 1
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portfolio
Portfolio item number 1
Short description of portfolio item number 1
Portfolio item number 2
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publications
APAC: An Accurate and Adaptive Prefetch Framework with Concurrent Memory Access Analysis
Published in The 2020 IEEE 39th International Conference on Computer Design (ICCD 2020), 2020
Background
CoPIM: A Concurrency-aware PIM Workload Offloading Architecture for Graph Applications
Published in The 2021 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2021), 2021
Background
Premier: A Concurrency-Aware Pseudo-Partitioning Framework for Shared Last-Level Cache
Published in The 2021 IEEE 39th International Conference on Computer Design (ICCD 2021), 2021
Background
A generalized model for modern hierarchical memory system
Published in 2022 Winter Simulation Conference (WSC 2022), 2022
Abstract
The Memory-Bounded Speedup Model and its Impacts in Computing
Published in Journal of Computer Science and Technology (JCST), 2023
Abstract
With the surge of big data applications and the worsening of the memory-wall problem, the memory system, instead of the computing unit, becomes the commonly recognized major concern of computing. However, this “memory-centric” common understanding has a humble beginning. More than three decades ago, the memory-bounded speedup model is the first model recognizing memory as the bound of computing and provided a general bound of speedup and a computing-memory trade-off formulation. The memory-bounded model was well received even by then. It was immediately introduced in several advanced computer architecture and parallel computing textbooks in the 1990’s as a must-know for scalable computing. These include Prof. Kai Hwang’s book “Scalable Parallel Computing” in which he introduced the memory-bounded speedup model as the Sun-Ni’s Law, parallel with the Amdahl’s Law and the Gustafson’s Law. Through the years, the impacts of this model have grown far beyond parallel processing and into the fundamental of computing. In this article, we revisit the memory-bounded speedup model and discuss its progress and impacts in depth to make a unique contribution to this special issue, to stimulate new solutions for big data applications, and to promote data-centric thinking and rethinking.
CARE: A Concurrency-Aware Enhanced Lightweight Cache Management Framework
Published in The 29th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2023), 2024
Background
CHROME: Concurrency-Aware Holistic Cache Management Framework with Online Reinforcement Learning
Published in The 30th IEEE International Symposium on High-Performance Computer Architecture (HPCA 2024), 2024
Background
ACES: Accelerating Sparse Matrix Multiplication with Adaptive Execution Flow and Concurrency-Aware Cache Optimizations
Published in The 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2024), 2024
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AceMiner: Accelerating Graph Pattern Matching using PIM with Optimized Cache System
Published in The 2024 IEEE 42nd International Conference on Computer Design (ICCD 2024), 2024
Background
talks
Talk 1 on Relevant Topic in Your Field
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Conference Proceeding talk 3 on Relevant Topic in Your Field
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teaching
Teaching experience 1
Undergraduate course, University 1, Department, 2014
This is a description of a teaching experience. You can use markdown like any other post.
Teaching experience 2
Workshop, University 1, Department, 2015
This is a description of a teaching experience. You can use markdown like any other post.